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How to perform runtime error checking on Cortex-M devices

Posted by Magnus Unemyr on Dec 18, 2015 9:17:47 AM

Embedded development is difficult, and embedded debugging may be even more so. Thus it is important to use the best tools in your toolbox. It appears to me that many Cortex-M developers are not fully aware of the powerful debug capabilities included in their Cortex-M based microcontrollers, like STM32, Kinetis, LPC or EFM32. This is valid for the super-useful Serial Wire Viewer (SWV) real-time event and data tracing capabilities, but perhaps even more so, the hard fault crash analyzis capabilities integrated in the Cortex-M core.

For example, our Atollic TrueSTUDIO debugger includes a hard fault crash analyzer, which detects hard-to-find runtime errors during full-speed target execution. Perhaps your system crashes a couple of times every week due to a sensor reading out-of-range values, causing a pointer error to bring the CPU to a hard fault due to accessing illegal memory or on misaligned address  boundaries.  Or your code performs a division by zero, once a week. These types of problems can be really hard to find and solve.

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link, ST-LINK

Real-time "live" variable watch on Cortex-M processors [debugger tips]

Posted by Magnus Unemyr on Jul 28, 2015 11:38:00 AM

ARM Cortex-M processors like STM32, Kinetis or EFM32 support live variable watch, a debugger feature that update the variables in a watch view in (almost) real-time as the target system executes at full speed. This feature is incredibly useful and can quickly help identify many bugs. Still, it appears many Cortex-M developers are not aware of this important debug capability.

I wrote another blog post on this topic some months ago, but I keep getting questions on the subject so I will cover live "real-time" variable watch once more. I would argue this capability is so useful and important, that professional embedded developers should not use an IDE without this ability. Let’s see how live variable watch debugger windows can be useful.

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link, ST-LINK

ARM Cortex devices are increasingly becoming dual-core: Are you ready?

Posted by Magnus Unemyr on Jul 20, 2015 1:16:00 PM

More and more ARM Cortex devices are dual-core, such as NXP’s LPC4300 with its Cortex-M4 and Cortex-M0 combo, or Freescale’s Vybrid equipped with Cortex-A5 and Cortex-M4 cores. Embedded systems using dual-core devices are typically fairly sophisticated, with an increased application complexity, which increases debugging difficulties compared to single-core systems as well.

Embedded systems developers moving from single-core to dual-core devices then ask: How do you develop and debug an embedded system using a dual-core processor? From a code development point of view, it is fairly easy. Just create two different projects in your ARM Cortex C/C++ IDE, and create each application project as if the device was a single-core processor. But how to debug asymmetric dual-core devices where the cores are not even using the same CPU core?

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link

Attach to running target using SEGGER J-Link

Posted by Mattias Norlander on Jun 30, 2015 2:08:00 PM

INTRODUCTION:

Atollic technical support team are often asked how to make Atollic TrueSTUDIO connect to a running target in order to troubleshoot a crashed CPU. This article shows, step-by-step, how to connect to a running target without restting it.

This approach is useful when trying to resolve problems which occur at rare occasions, often after several days of running your embedded application, by connecting Atollic TrueSTUDIO debugger via JTAG/SWD the embedded target using a SEGGER J-Link.

Finding the root cause of the problem in case of a CPU crash is further simplified by learning how to use the Fault Analyzer view. White paper and Video tutorial is provided!

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link

What you need to know about debugging interrupts and exceptions on Cortex-M devices

Posted by Magnus Unemyr on Apr 28, 2015 11:20:34 AM

Any Cortex-M developer have likely struggled with getting interrupts to work, or tried to debug them. Getting it all hooked up can be rather tricky, from getting a correctly defined interrupt vector table linked on the right memory addresses, to enabling interrupts properly, and then processing them in an interrupt handler. It all involves advanced topics like linker configuration files, SFR register bit field configuration and manipulation, interrupt #pragmas, possibly inline assembly and more.

So how do you go about analyzing and debugging the behavior of your interrupts and exceptions on a Cortex-M device like STM32, Kinetis, LPC or EFM32? Interrupts and exceptions are by definition asynchronous to the execution flow of your application software and it can be very difficult to visualize interrupt behavior, and debug the same. So what is a Cortex-M developer to do? As it so happens, the Cortex-M core has brilliant hardware support for visualizing and debugging interrupt behavior. This is how to use it.

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link, ST-LINK

How to develop and debug BOOTLOADER + APPLICATION systems on ARM Cortex-M devices

Posted by Magnus Unemyr on Apr 27, 2015 4:21:00 PM

As we all painfully have come to learn - firmware is rarely bug-free and new requirements are usually added over time. And so there is a need for a method to upgrade the firmware of a shipped product when defects are found or new functionality is needed. From a logistics point of view, a product recall with a factory upgrade might not be a feasible option.

By separating the application logic from the booting process, developers can design a system that allows end-users or service technicians to upgrade the application software with a newer and presumably better version later on, without the need for recalls or factory upgrades. This can be done using a bootloader. But what is a bootloader and how is it implemented and debugged on an ARM Cortex-M device like STM32 or Kinetis? The post also links to a bootloader code example for STM32F4-Discovery.

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link, ST-LINK

New whitepaper on ETM/ETB instruction tracing on Cortex-M devices

Posted by Magnus Unemyr on Apr 23, 2015 2:19:57 PM

As outlined in a recent blog article, ETM/ETB instruction tracing is the heavy artillery in Cortex-M debugging, and you may need it to solve that impossible "one million dollar bug", or if you cannot stop on breakpoints without damaging physical equipment, which can be the case in motor control applications for example.

Using ETM/ETB instruction tracing, you can record execution history for later analysis, and thus work out what the CPU did prior to the bug. To do that, you need an ETM-trace enabled debug probe, such as the SEGGER J-Trace, as well as a debugger IDE like Atollic TrueSTUDIO with trace support. For ETB, no particular trace-enabled debugger probe is needed, but the target device needs to have ETB on-chip. You can read more on ETM/ETB instruction tracing on Cortex-M devices like STM32, Kinetis or LPC in our new whitepaper.

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link

Why STM32 developers still need an SFR view to study the STM32 special function peripheral registers

Posted by Magnus Unemyr on Apr 20, 2015 11:08:55 AM

Writing device-drivers for microcontrollers like STM32 is very complicated if you haven’t written a few of them before; not only do you need to understand the peripheral module hardware and their special function registers (SFR’s), you also have to be an ace on the meaning of SFR bit-fields and bits, understand interrupt vector tables, #pragmas, inline assembly and other intricate things.

Not too many years ago, semiconductor vendors didn’t provide device-driver libraries with their microcontrollers, and so each customer had to write them from scratch. What a waste of engineering time and duplication of resources! Way too many years later, they started to ship static device driver libraries or device-driver generations tools to help struggling developers. STMicroelectronics for example provide both static STM32 device-driver libraries, as well as the STM32CubeMX device initialization tool. And so, with readymade device driver libraries available, do STM32 developers need to worry about SFR’s anymore? I’d say yes, for reasons outlined in this blog article.

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link, ST-LINK

Using SEGGER J-Trace to record and analyze execution history with ETM instruction tracing

Posted by Magnus Unemyr on Apr 16, 2015 2:02:00 PM

The Segger J-Link and other JTAG/debug probes (like ST-LINK for STM32 devices) offer great debugging capabilities on ARM Cortex-M devices, such as STM32, EFM32, XMC or Kinetis. Debugging techniques supported by J-Link and ST-LINK include for example hard fault crash analysis and real-time system analysis with event- and data tracing using the Serial Wire Viewer (SWV) interface.

This is great, but what if you are still stuck? Or perhaps you will damage physical H/W if you stop execution on a breakpoint, which can be the case in motor control applications. In such case, you may need to call for the heavy debugging artillery. For ARM Cortex developers, that means bringing in a debug probe that can record execution history for later analysis, using the ETM instruction trace interface from ARM. To do that, you need an ETM-trace enabled debug probe, such as the SEGGER J-Trace, as well as a debugger IDE like Atollic TrueSTUDIO with trace support..

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link

Is SEGGER J-Link the best debugger probe for ARM Cortex debugging?

Posted by Magnus Unemyr on Apr 10, 2015 1:37:00 PM

SEGGER J-Link’s are probably the most widely used line of debugger probes available today, at least within the world of ARM, and in particular for ARM Cortex-M devices like STM32 or Kinetis. SEGGER claims to have shipped over 250.000 JTAG probes over the years. I cannot verify if this is true or not, but most professional engineering teams I have met doing STM32 development are using the SEGGER J-Link for example, and so I see no reason to question that figure.

I have even heard the J-Link name been used synonymous to a debugger probe in general (from any vendor) multiple times. As such, SEGGER has almost succeeded in getting the J-Link name being the industry standard reference, much like Google have managed to get its company name being equal to do an internet search in general (“to google something”). So what about these SEGGER debugger probes anyway?

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Topics: ARM Cortex, Debugging, Atollic TrueSTUDIO, SEGGER J-Link

Meet STM32F7 – The new Cortex-M7 based STM32 family

Posted by Magnus Unemyr on Apr 10, 2015 11:49:00 AM

The new ARM Cortex-M7 processor core is the most recent and highest performance of the different microcontroller cores in the ARM Cortex-M family. And as such, it outperforms for example the Cortex-M3 and Cortex-M4 on performance, while maintaining backwards compatibility.

Many semiconductor manufacturers have announced new Cortex-M7 devices, and one of the first out is STMicroelectronics, adding new Cortex-M7 devices to their STM32 family. The Cortex-M7 version of STM32 is called STM32F7, runs at 200MHz and initially coming with 512KB or 1MB of Flash memory and 320KB of RAM. And so, what can STM32 developers expect, when equipping their coming designs with the more powerful STM32F7?

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Topics: ECLIPSE, ARM Cortex, GNU tools (GCC/GDB), Atollic TrueSTUDIO, SEGGER J-Link, ST-LINK

Cortex-M debugging: Measure execution time using SWV/ITM

Posted by Magnus Unemyr on Apr 10, 2015 10:22:00 AM

By now, I have written a large number of blog articles highlighting the advanced debugger capabilities offered by the Serial Wire Viewer (SWV) real-time event- and data tracing, available in Cortex-M devices, such as STM32 from STMicroelectronics, Kinetis from Freescale, LPC from NXP, etc. In this blog article, I will mention how the Instrumentation Trace Macrocell (ITM), which is part of SWV, can be used to measure the execution time of any-sized and any-partitioned blocks of code.

For example, you may want to know what the execution time is of a while{} loop. Or how long it takes from the user press the “Heat” button until the oven reaches a certain temperature in the code (perhaps detected by an if{} statement code line), or how long time it takes to execute 15 sequential lines  of code in a function. All these time measurement use cases, and more, can easily be accommodated using SWV/ITM in Cortex-M based devices, such as the widely popular STM32 or Kinetis microcontroller families.

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Topics: ECLIPSE, ARM Cortex, GNU tools (GCC/GDB), Debugging, Atollic TrueSTUDIO, SEGGER J-Link, ST-LINK